For the 32 nanometer (nm) technology node, source/drain regions in a PMOS semiconductor element are typically formed of 20% eSiGe, i.e., eSiGe with 20 at. % germanium (Ge), and exhibit enhanced channel strain thereby increasing hole mobility for increased speed. Boron (B) is typically introduced as a dopant to reduce contact resistance. Adverting to FIG. 1, cavities 101, defined by spacers 105, made of oxide or nitride, are formed in an active silicon layer 103 on each side of semiconductor gate 107, as by reactive ion etching. Silicon germanium (SiGe) is then epitaxially grown in the cavities 101 and doped with B. A silicide layer 109 is then formed on the SiGe, using a spacer, such as silicon nitride (SiN) spacer 111 as a mask. As illustrated in FIG. 1, silicide layer 109 in the 20% eSiGe is well-contained, has a uniform thickness, and lines up along the SiN spacer 111.
However, Boron solubility in 20% eSiGe is low, for example a concentration of less than 1E20 cm-3 for chemical boron and about 5E19 cm-3 for electrically active Boron. It would be desirable to increase the amount of Ge to at least 30 at. % to achieve higher B solubility, e.g., greater than 5E20 cm-3 for chemical B (which is about five times greater than in 20% eSiGe) and about 2E20 cm-3 for electrically active B (which is about four times greater than in 20% eSiGe). The high active B concentration provides a low silicide-to-eSiGe contact resistance (Rc). For example, 20% eSiGe has a value of Rc that is 2 to 3 times that of 30% eSiGe. In addition, 30% eSiGe has a higher strain than 20% eSiGe, e.g., about a 50% increase in strain. Thus, 30% eSiGe provides two desirable benefits over 20% eSiGe, i.e., enhanced channel mobility by enhancing channel strain, and reduced silicide-to-eSiGe Rc.
However, there are significant disadvantages attendant upon employing 30% eSiGe compared with 20% eSiGe. Adverting to FIG. 2, when 30% eSiGe is used for the source/drain regions 201, the silicide 203 is no longer well contained along the SiN spacer, but encroaches vertically (207) as well as laterally (205), thereby undesirably reducing channel stress and causing source-drain to channel junction leakage. Whereas the depth of the silicide is normally about 200 Å in 20% eSiGe, the depth in 30% eSiGe extends approximately an additional 100 Å from the bottom of the SiN spacer. Further, variations on the right side of the gate differ from those on the left side. The uncontrollable silicide depth and width causes eSiGe strain relaxation and creates silicide pipes at the eSiGe-to-silicon interface, thereby causing junction leakage.
A proposed solution to mitigate the silicide encroachment issue is illustrated in FIG. 3, and comprises growing a region of 30% eSiGe (301) as to a thickness of about 400 angstroms (Å) to about 800 Å, e.g., about 600 Å, and then growing a layer 303 of 20% eSiGe on the 30% eSiGe region, as to a thickness of about 200 Å to about 400 Å. As shown in FIG. 3, silicide 305 formed in the 20% eSiGe portion is well contained, with a uniform thickness and no lateral or vertical encroachment. However, 20% eSiGe exhibits significantly less strain than 30% eSiGe, thereby reducing channel mobility. In addition, active B in 20% eSiGe is limited to less than 6E19 cm-3, resulting in high silicide-to-eSiGe Rc. To lower the Rc, the active B concentration must be raised to at least 2E20 cm-3, which requires implanting B. However, implantation of B causes undesirable strain relaxation. Further, implanted B requires high temperature rapid thermal anneal (RTA), e.g., about 900° C. to about 1300° C., for activation, resulting in significant B diffusion that can overrun the extension and degrade the device short channel control. In contrast, high concentration (about 2 to 5e20 cm-3) B incorporated in situ is already active and, therefore, only requires low temperature RTA, e.g., about 900° C. to about 1000° C.
A need therefore exists for semiconductor devices having eSiGe source/drain regions with well contained silicide without lateral and vertical encroachment, and which exhibit high strain, enhanced channel mobility, and low silicide-to-eSiGe Rc, and for efficient enabling fabrication techniques.